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HT47C20L
R-F Type Low Voltage 8-Bit Mask MCU
Technical Document
* Tools Information * FAQs * Application Note -
HA0029E HA0030E HA0034E HA0036E HA0045E
Using the Time Base Function in the HT47R20A-1 Using the RTC in the HT47R20A-1 Using the Buzzer Function in the HT47R20A-1 Using the PFD Function in the HT47R20A-1 Distinguishing between the Different Devices in the HT47 MCU Series
Features
* Operating voltage: 1.2V~2.2V * Eight bidirectional I/O lines * Four input lines * One interrupt input * One 16-bit programmable timer/event counter with * One low voltage reset circuit * HALT function and wake-up feature reduce power
consumption
* LCD bias C type * One LCD driver with 202 or 203 or 194 segments * Two channels RC type A/D converter * Four-level subroutine nesting * Bit manipulation instruction * 16-bit table read instruction * Up to 122ms instruction cycle with 32768Hz system
PFD (programmable frequency divider) function
* On-chip 32768Hz crystal oscillator * Watchdog Timer * 2K16 program memory ROM * 648 data memory RAM * One real time clock (RTC) * One 8-bit prescaler for real time clock * One buzzer output * One low voltage detector
clock
* All instructions in one or two machine cycles * 63 powerful instructions * 64-pin QFP package
General Description
The HT47C20L is an 8-bit high performance RISC-like microcontroller. Its single cycle instruction and two-stage pipeline architecture make high speed applications. The device is suited for use in multiple LCD low power applications among which are calculators, clock timers, games, scales, toys, thermometers, hygrometers, body thermometers, capacitor scaler, other hand held LCD products, and battery system in particular.
Rev. 2.30
1
December 2, 2005
HT47C20L
Block Diagram
P B 0 /IN T
P ro g ra m ROM
P ro g ra m C o u n te r
ST ST ST ST
AC AC AC AC
K0 K1 K2 K3
In te rru p t C ir c u it
T im e r A
M U
X
IN T C PFD T im e r B A /D
S y s te m C lo c k T1 R T C O u tp u t P B 2 /T M R P B 3 /P F D C lo c k IN 0 CS RS CR RT IN 1 CS RS RT 0 1 1 1 0 0 T0
In s tr u c tio n R e g is te r
MP
M U
X
DATA M e m o ry
RC Type A /D C o n v e rte r
In s tr u c tio n D ecoder ALU T im in g G e n e ra to r
MUX R e a l T im e C lo c k STATUS W DT T im e B a s e BP P o rt B PB P B 0 /IN T PB1 P B 2 /T M R PB3 P o rt A PA PA PA PA PA PA 0 /B 1 /B 2 3 /P 4~P Z Z FD A7 32768H z ( a lw a y s o n )
S h ifte r
OSC2
OS RE VD VS S
D
S
C1
ACC LCD M e m o ry L C D D r iv e r
C1 C2
D o u b le V o lta g e
V1
V2
V3
C O M 0~ COM2
C O M 3/ SEG 19
SEG 0~ SEG 18
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HT47C20L
Pin Assignment
OSC2 OSC1 VDD RES NC
NC
P A 0 /B Z
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
64 63 62 61 60 59 58 57 56 55 54 53 52
NC
NC
C1
C2
V1
V2
V3 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG 10 SEG 11 SEG 12 SEG 13 SEG 14 SEG 15 SEG 16 SEG 17 SEG 18
P A 1 /B Z PA2 P A 3 /P F D PA4 PA5 PA6 PA7 P B 0 /IN T PB1 P B 2 /T M R PB3 NC TEST NC NC NC NC VSS
H T47C 20L 6 4 Q F P -A
20 21 22 23 24 25 26 27 28 29 30 31 32
RS0
CS0
IN 0
COM0
COM1
COM2
C O M 3 /S E G 1 9
RT0
RS1
CS1
IN 1
CRT0
RT1
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HT47C20L
Pin Description
Pin Name RES PA0/BZ PA1/BZ PA2 PA3/PFD PA4~PA7 PB0/INT PB1 PB2/TMR PB3 VSS V1~V3, C1~C2 SEG19/COM3 COM2~COM0 SEG18~SEG0 VDD OSC2 OSC1 IN0 CS0 RS0 CRT0 RT0 IN1 CS1 RS1 RT1 TEST I/O I Mask Option 3/4 Wake-up Pull-high or None CMOS or NMOS Function Schmitt trigger reset input. Active low. Bidirectional 8-bit input/output port. The low nibble of the PA can be configured as CMOS output or NMOS output with or without pull-high resistors (mask option). NMOS output can be configured as Schmitt trigger input with or without pull-high resistors. Each bit of NMOS output can be configured as wake up input by mask option. Of the eight bits, PA0~PA1 can be set as I/O pins or buzzer outputs by mask option. PA3 can be set as an I/O pin or a PFD output by mask option. Four-bit Schmitt trigger input port. The PB is configured as with pull-high resistors. Of the four bits, PB0 can be set as an input pin or an external interrupt input pin (INT) by software application. While PB2 can be set as an input pin or a timer/event counter input pin by software application. Negative power supply, ground Voltage pump
I/O
I
3/4
3/4 3/4 O O 3/4 O I I O O O O I O O O I
3/4 3/4
1/2 or 1/3 or 1/4 SEG19/COM3 can be set as a segment or a common output driver for LCD Duty panel by mask option. COM2~COM0 are outputs for LCD panel plate. 3/4 3/4 3/4 LCD driver outputs for LCD panel segments Positive power supply OSC1 and OSC2 are connected to a 32768Hz crystal for the internal system clock and WDT source. Oscillation input pin of channel 0 Reference capacitor connection pin of channel 0 Reference resistor connection pin of channel 0 Resistor/capacitor sensor connection pin for measurement of channel 0 Resistor sensor connection pin for measurement of channel 0 Oscillation input pin of channel 1 Reference capacitor connection pin of channel 1 Reference resistor connection pin of channel 1 Resistor sensor connection pin for measurement of channel 1 TEST mode input pin with pull-high resistor. It disconnects in normal operation.
3/4
3/4
3/4
Absolute Maximum Ratings
Supply Voltage ...........................VSS-0.3V to VSS+2.5V Input Voltage..............................VSS-0.3V to VDD+0.3V Storage Temperature ............................-50C to 125C Operating Temperature...........................-40C to 85C
Note: These are stress ratings only. Stresses exceeding the range specified under Absolute Maximum Ratings may cause substantial damage to the device. Functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability.
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HT47C20L
D.C. Characteristics
Symbol VDD VLVD VLVR IDD1 IDD2 IDD3 Parameter Operating Voltage Low Voltage Detector Voltage Low Voltage Reset Voltage Operating Current (LVR Disable, LVD Disable) Operating Current (LVR Disable, LVD Enable) Operating Current (LVR Enable, LVD Enable) Test Conditions VDD 3/4 3/4 3/4 1.5V 1.5V 1.5V Conditions 3/4 3/4 3/4 No load, fSYS=32768Hz A/D Off, LVD Off No load, fSYS=32768Hz A/D Off, LVD Off No load, fSYS=32768Hz A/D Off, LVD Off Min. 1.2 1.1 1.0 3/4 3/4 3/4 3/4 Typ. 1.5 1.2 1.1 4 9 12 Max. 2.2 1.3 1.2 8 15 20 Ta=25C Unit V V V mA mA mA mA
ISTB1
Standby Current No load, system HALT (Mask Option Select LVR Disable, LVD Dis- 1.5V A/D Off, LVD Off able, LCD Off) Standby Current No load, system HALT (Mask Option Select LVR Disable, LVD 1.5V A/D Off, LVD Off Enable, LCD On or Off) Standby Current No load, system HALT (Mask Option Select LVR Enable, LVD 1.5V A/D Off, LVD Off Enable, LCD On or Off) Standby Current No load, system HALT (Mask Option Select LVR Disable, LVD 1.5V A/D Off, LVD On Enable, LCD On or Off) Additional Power Consumption if A/D is 1.5 Used Input Low Voltage for I/O Ports Input High Voltage for I/O Ports Input Low Voltage (RES) Input Low Voltage (INT, TMR) Input High Voltage (RES, INT, TMR) I/O Port Sink Current I/O Port Source Current Common 0~3 Output Sink Current Common 0~3 Output Source Current Segment 0~19 Output Sink Current Segment 0~19 Output Source Current Common 0~3 Output Sink Current Common 0~3 Output Source Current Segment 0~19 Output Sink Current Segment 0~19 Output Source Current RC oscillation Output Sink Current RC oscillation Output Source Current 3/4 3/4 3/4 3/4 3/4 1.5V VOL=0.15V 1.5V VOH=1.35V 1.5V VOL=0.3V (1/2bias) 1.5V VOH=2.7V (1/2bias) 1.5V VOL=0.3V (1/2bias) 1.5V VOH=2.7V (1/2bias) 1.5V VOL=0.45V (1/3bias) 1.5V VOH=4.05V (1/3bias) 1.5V VOL=0.45V (1/3bias) 1.5V VOH=4.05V (1/3bias) 1.5V VOL=0.15V 1.5V VOH=1.35V 3/4 3/4 A/D On *R=5.1kW, *C=500pF 3/4 3/4 3/4 3/4 3/4
1
2
ISTB2
3/4
6
10
mA
ISTB3
3/4
9
15
mA
ISTB4
3/4 3/4 0 0.8VDD 0 0 0.8VDD 0.3 -0.2 120 -50 30 -20 120 -50 30 -20 2 -2 100 10
8
15
mA mA V V V V V mA mA mA mA mA mA mA mA mA mA mA mA kW kW
IAD VIL VIH VIL1 VIL2 VIH1 IOL IOH IOL1 IOH1 IOL2 IOH2 IOL3 IOH3 IOL4 IOH4 IOL5 IOH5 RPH1 RPH2 Note:
270 3/4 3/4 3/4 3/4 3/4 0.6 -0.4 230 -100 60 -30 220 -100 60 -30 2.7 -3.1 150 30
500 0.3VDD VDD 0.5VDD 0.3VDD VDD 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 200 60
Pull-high Resistance of I/O Ports and INT 1.5V Pull-high Resistance of TEST 1.5V
*R means the resistance of RC type A/D converter *C means the capacitance of RC type A/D converter
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HT47C20L
A.C. Characteristics
Symbol fSYS1 fTIMER tRES tSST tINT tRIS tLVD fAD System Clock Timer I/P Frequency (TMR) External Reset Low Pulse Width System Start-up Timer Period Interrupt Pulse Width Power Supply Rise Time Low Voltage Detector Response Time A/D Converter Frequency Parameter Test Conditions VDD 1.5V 1.5V 3/4 3/4 1.5V 3/4 1.5V 1.5V Conditions 3/4 3/4 3/4 3/4 3/4 Power-up 3/4 3/4 Min. 3/4 0 100 3/4 100 3/4 200 3/4 Typ. 32768 3/4 3/4 8192 3/4 3/4 3/4 3/4 Max. 3/4 32768 3/4 3/4 3/4 1 3/4 500 Ta=25C Unit Hz Hz ms tSYS ms s ms kHz
Note: tSYS=1/fSYS
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HT47C20L
Functional Description
Execution Flow The HT47C20L system clock is derived from a 32768Hz crystal oscillator. The system clock is internally divided into four non-overlapping clocks (T1, T2, T3 and T4). One instruction cycle consists of four system clock cycles. Instruction fetching and execution are pipelined in such a way that a fetch takes one instruction cycle while decoding and execution takes the next instruction cycle. However, the pipelining scheme causes each instruction to effectively execute in one cycle. If an instruction changes the program counter, two cycles are required to complete the instruction. Program Counter - PC The 11-bit program counter (PC) controls the sequence in which the instructions stored in the program ROM are executed and its contents specify a maximum of 2048 addresses. After accessing a program memory word to fetch an instruction code, the contents of the program counter are
T1 T2 T3 T4 T1 T2 T3 T4 T1 T2 T3 T4
incremented by 1. The program counter then points to the memory word containing the next instruction code. When executing a jump instruction, conditional skip execution, loading PCL register, subroutine call, initial reset, internal interrupt, external interrupt or return from subroutine, the PC manipulates the program transfer by loading the address corresponding to each instruction. The conditional skip is activated by instruction. Once the condition is met, the next instruction, fetched during the current instruction execution, is discarded and a dummy cycle replaces it to get the proper instruction. Otherwise proceed with the next instruction. The lower byte of the program counter (PCL) is a readable and writeable register (06H). Moving data into the PCL performs a short jump. The destination will be within 256 locations. When a control transfer takes place, an additional dummy cycle is required.
S y s te m
C lo c k
In s tr u c tio n C lo c k
PC
PC
PC+1
PC+2
F e tc h IN S T (P C ) E x e c u te IN S T (P C -1 )
F e tc h IN S T (P C + 1 ) E x e c u te IN S T (P C )
F e tc h IN S T (P C + 2 ) E x e c u te IN S T (P C + 1 )
Execution Flow Program Counter *10 0 0 0 0 0 *10 #10 S10 *9 0 0 0 0 0 *9 #9 S9 *8 0 0 0 0 0 *8 #8 S8 *7 0 0 0 0 0 @7 #7 S7 *6 0 0 0 0 0 @6 #6 S6 *5 0 0 0 0 0 @5 #5 S5 *4 0 0 0 0 1 @4 #4 S4 *3 0 0 1 1 0 @3 #3 S3 *2 0 1 0 1 0 @2 #2 S2 *1 0 0 0 0 0 @1 #1 S1 *0 0 0 0 0 0 @0 #0 S0
Mode Initial Reset External Interrupt Time Base Interrupt Real Time Clock Interrupt Timer/event Counter Interrupt Skip Loading PCL Jump, Call Branch Return from Subroutine
Program Counter+2
Program Counter Note: *10~*0: Program counter bits S10~S0: Stack register bits #10~#0: Instruction code bits @7~@0: PCL bits
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HT47C20L
Program Memory - ROM The program memory is used to store the program instructions which are to be executed. It also contains data, table, and interrupt entries, and is organized into 204816 bits, addressed by the program counter and table pointer. Certain locations in the program memory are reserved for special usage:
* Location 000H * Location 00CH
This area is reserved for the real time clock interrupt service program. If a real time clock interrupt occurs, and if the interrupt is enabled and the stack is not full, the program begins execution at location 00CH.
* Location 010H
This area is reserved for the initialization program. After chip reset, the program always begins execution at location 000H.
* Location 004H
This area is reserved for the timer/event counter interrupt service program. If timer interrupt results from a Timer/Event Counter A or B overflow, and if the interrupt is enabled and the stack is not full, the program begins execution at location 010H.
* Table location
This area is reserved for the external interrupt service program. If the INT input pin is activated, and the interrupt is enabled and the stack is not full, the program begins execution at location 004H.
* Location 008H
This area is reserved for the time base interrupt service program. If time base interrupt resulting from a time base overflow, and if the interrupt is enabled and the stack is not full, the program begins execution at location 008H.
000H 004H 008H
00CH 010H D e v ic e in itia liz a tio n p r o g r a m E x te r n a l in te r r u p t s u b r o u tin e T im e B a s e In te r r u p t s u b r o u tin e R e a l T im e C lo c k In te r r u p t s u b r o u tin e P ro g ra m ROM
T im e r /e v e n t C o u n te r in te r r u p t s u b r o u tin e
n00H nFFH
L o o k - u p ta b le ( 2 5 6 w o r d s )
Any location in the ROM space can be used as look-up tables. The instructions TABRDC [m] (the current page, 1 page=256 words) and TABRDL [m] (the last page) transfer the contents of the lower-order byte to the specified data memory, and the higher-order byte to TBLH (08H). Only the destination of the lower-order byte in the table is well-defined, the higher-order byte of the table word are transferred to the TBLH. The table higher-order byte register (TBLH) is read only. The table pointer (TBLP) is a read/write register (07H), which indicates the table location. Before accessing the table, the location must be placed in TBLP. The TBLH is read only and cannot be restored. If the main routine and the ISR (interrupt service routine) both employ the table read instruction, the contents of the TBLH in the main routine are likely to be changed by the table read instruction used in the ISR. Errors can occur. In other words using the table read instruction in the main routine and the ISR simultaneously should be avoided. However, if the table read instruction has to be applied in both the main routine and the ISR, the interrupt is supposed to be disabled prior to the table read instruction. It will not be enabled until the TBLH has been backed up. All table related instructions need two cycles to complete the operation. These areas may function as normal program memory depending upon the requirements. Stack Register - STACK
7FFH
L o o k - u p ta b le ( 2 5 6 w o r d s ) 1 6 b its
N o te : n ra n g e s fro m
0 to 7
Program Memory
This is a special part of the memory which is used to save the contents of the Program Counter only. The stack is organized into four levels and is neither part of the data nor part of the program space, and is neither readable nor writeable. The activated level is indexed by the Table Location
Instruction(s) TABRDC [m] TABRDL [m]
*10 P10 1
*9 P9 1
*8 P8 1
*7 @7 @7
*6 @6 @6
*5 @5 @5
*4 @4 @4
*3 @3 @3
*2 @2 @2
*1 @1 @1
*0 @0 @0
Table Location Note: *10~*0: Bits of table location P10~P8: Bits of current program counter Rev. 2.30 8 December 2, 2005 @7~@0: Bits of table pointer
HT47C20L
stack pointer (SP) and is neither readable nor writeable. At a subroutine call or interrupt acknowledgment, the contents of the program counter are pushed onto the stack. At the end of a subroutine or an interrupt routine, signaled by a return instruction (RET or RETI), the program counter is restored to its previous value from the stack. After a chip reset, the SP will point to the top of the stack. If the stack is full and a non-masked interrupt takes place, the interrupt request flag will be recorded but the acknowledgment will be inhibited. When the stack pointer is decremented (by RET or RETI), the interrupt will be serviced. This feature prevents stack overflow allowing the programmer to use the structure more easily. In a similar case, if the stack is full and a CALL is subsequently executed, stack overflow occurs and the first entry will be lost (only the most recent four return addresses are stored). Data Memory - RAM The data memory is designed with 838 bits. The data memory is divided into two functional groups: special function registers and general purpose data memory (648). Most are read/write, but some are read only. The special function registers include the indirect addressing register 0 (00H), the memory pointer register 0 (MP0; 01H), the indirect addressing register 1 (02H), the memory pointer register 1 (MP1;03H), the bank pointer (BP;04H), the accumulator (ACC;05H), the program counter lower-order byte register (PCL;06H), the table pointer (TBLP;07H), the table higher-order byte register (TBLH;08H), the real time clock control register (RTCC;09H), the status register (STATUS;0AH), the interrupt control register 0 (INTC0;0BH), the I/O registers (PA;12H, PB;14H), the interrupt control register 1 (INTC1;1EH), the Timer/Event counter A higher order byte register (TMRAH; 20H), the Timer/Event Counter A lower order byte register (TMRAL; 21H), the timer/event counter control register (TMRC; 22H), the Timer/Event Counter B higher order byte register (TMRBH; 23H), the Timer/Event Counter B lower-order byte register (TMRBL; 24H), and the RC oscillator type A/D converter control register (ADCR; 25H). The remaining space before the 40H are reserved for future expanded usage and reading these location will return the result 00H. The general purpose data memory, addressed from 40H to 7FH, is used for data and control information under instruction command. All data memory areas can handle arithmetic, logic, increment, decrement and rotate operations. Except for some dedicated bits, each bit in the data memory can be set and reset by the SET [m].i and CLR [m].i instruction, respectively. They are also indirectly accessible through memory pointer registers (MP0;01H, MP1;03H).
00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH 20H 21H 22H 23H 24H 25H 26H 3FH 40H G e n e ra l P u rp o s e D a ta M e m o ry (6 4 B y te s ) 7FH IN T C 1 TM RAH TM RAL TM RC TM RBH TM RBL ADCR :U nused PB PA S p e c ia l P u r p o s e D a ta M e m o ry In d ir e c t A d d r e s s in g R e g is te r 0 MP0 In d ir e c t A d d r e s s in g R e g is te r 1 MP1 BP ACC PCL TBLP TBLH RTCC STATUS IN T C 0
R e a d a s "0 0 "
RAM Mapping (Bank 0) Indirect Addressing Register Location 00H and 02H are indirect addressing registers that are not physically implemented. Any read/write operation of [00H] and [02H] access data memory pointed to by MP0 (01H) and MP1 (03H) respectively. Reading location 00H or 02H indirectly will return the result 00H. Writing indirectly results in no operation.
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HT47C20L
The function of data movement between two indirect addressing registers are not supported. The memory pointer registers, MP0 and MP1, are both 8-bit registers which can be used to access the data memory by combining corresponding indirect addressing registers. MP0 only can be applied to data memory, while MP1 can be applied to data memory and LCD display memory. Accumulator The accumulator is closely related to ALU operations. It is also mapped to location 05H of the data memory and is capable of carrying out immediate data operations. The data movement between two data memory locations must pass through the accumulator. Arithmetic and Logic Unit - ALU This circuit performs 8-bit arithmetic and logic operation. The ALU provides the following functions:
* Arithmetic operations (ADD, ADC, SUB, SBC, DAA) * Logic operations (AND, OR, XOR, CPL) * Rotation (RL, RR, RLC, RRC) * Increment and Decrement (INC, DEC) * Branch decision (SZ, SNZ, SIZ, SDZ ....)
register will not change the TO or PDF flags. In addition it should be noted that operations related to the status register may give different results from those intended. The TO and PDF flags can only be changed by the Watchdog Timer overflow, system power-up, clearing the Watchdog Timer and executing the HALT instruction. The Z, OV, AC and C flags generally reflect the status of the latest operations. In addition, on entering the interrupt sequence or executing the subroutine call, the status register will not be automatically pushed onto the stack. If the contents of status are important and if the subroutine can corrupt the status register, precautions must be taken to save it properly. Interrupts The HT47C20L provides an external interrupt, an internal timer/event counter interrupt, an internal time base interrupt, and an internal real time clock interrupt. The interrupt control register 0 (INTC0;0BH) and interrupt control register 1 (INTC1;1EH) both contain the interrupt control bits to set the enable/disable and interrupt request flags. Once an interrupt subroutine is serviced, all other interrupts will be blocked (by clearing the EMI bit). This scheme may prevent any further interrupt nesting. Other interrupt requests may happen during this interval, but only the interrupt request flag is recorded. If a certain interrupt needs servicing within the service routine, the programmer may set the EMI bit and the corresponding bit of INTC0 or INTC1 allow interrupt nesting. If the stack is full, the interrupt request will not be acknowledged, even if the related interrupt is enabled, until the SP is decremented. If immediate service is desired, the stack must be prevented from becoming full.
The ALU not only saves the results of a data operation but can change the status register. Status Register - STATUS This 8-bit register (0AH) contains the zero flag (Z), carry flag (C), auxiliary carry flag (AC), overflow flag (OV), power down flag (PDF) and watchdog time-out flag (TO). It also records the status information and controls the operation sequence. With the exception of the TO and PDF flags, bits in the status register can be altered by instructions like most other registers. Any data written into the status Bit No. 0 Label C
Function C is set if the operation results in a carry during an addition operation or if a borrow does not take place during a subtraction operation; otherwise C is cleared. C is also affected by a rotate through carry instruction. AC is set if the operation results in a carry out of the low nibbles in addition or no borrow from the high nibble into the low nibble in subtraction; otherwise AC is cleared. Z is set if the result of an arithmetic or logic operation is 0; otherwise Z is cleared. OV is set if the operation results in a carry into the highest-order bit but not a carry out of the highest-order bit, or vice versa; otherwise OV is cleared. PDF is cleared when either a system power-up or executing the CLR WDT instruction. PDF is set by executing the HALT instruction. TO is cleared by a system power-up or executing the CLR WDT or HALT instruction. TO is set by a WDT time-out. Unused bit, read as 0 Unused bit, read as 0 STATUS (0AH) Register
1 2 3 4 5 6 7
AC Z OV PDF TO 3/4 3/4
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All these kinds of interrupt have a wake-up capability. As an interrupt is serviced, a control transfer occurs by pushing the program counter onto the stack, followed by a branch to a subroutine at specified locations in the program memory. Only the program counter is pushed onto the stack. If the contents of the register and status register (STATUS) is altered by the interrupt service program which corrupts the desired control sequence, the contents must be saved first. External interrupt is triggered by a high to low transition of INT and the related interrupt request flag (EIF; bit 4 of INTC0) will be set. When the interrupt is enabled, and the stack is not full and the external interrupt is active, a subroutine call to location 04H will occur. The interrupt request flag (EIF) and EMI bits will be cleared to disable other interrupts. The internal timer/event counter interrupt is initialized by setting the timer/event counter interrupt request flag (TF; bit 4 of INTC1), caused by a timer A or timer B overflow. When the interrupt is enabled, and the stack is not full and the TF bit is set, a subroutine call to location 10H will occur. The related interrupt request flag (TF) will be reset and the EMI bit cleared to disable further interrupts. The time base interrupt is initialized by setting the time base interrupt request flag (TBF; bit 5 of INTC0), caused by a regular time base signal. When the interrupt is enabled, and the stack is not full and the TBF bit is set, a subroutine call to location 08H will occur. The related interrupt request flag (TBF) will be reset and the EMI bit cleared to disable further interrupts. Bit No. 0 1 2 3 4 5 6 7 Label EMI EEI ETBI ERTI EIF TBF RTF 3/4 The real time clock interrupt is initialized by setting the real time clock interrupt request flag (RTF; bit 6 of INTC0), caused by a regular real time clock signal. When the interrupt is enabled, and the stack is not full and the RTF bit is set, a subroutine call to location 0CH will occur. The related interrupt request flag (RTF) will be reset and the EMI bit cleared to disable further interrupts. During the execution of an interrupt subroutine, other interrupt acknowledgments are held until the RETI instruction is executed or the EMI bit and the related interrupt control bit are set to 1 (if the stack is not full). To return from the interrupt subroutine, RET or RETI instruction may be invoked. RETI will set the EMI bit to enable an interrupt service, but RET does not. Interrupts occurring in the interval between the rising edges of two consecutive T2 pulses, will be serviced on the latter of the two T2 pulses, if the corresponding interrupts are enabled. In the case of simultaneous requests the following table shows the priority that is applied. These can be masked by resetting the EMI bit. No. a b c d Interrupt Source External Interrupt Time Base Interrupt Real Time Clock Interrupt Timer/event Counter Interrupt Priority Vector 1 2 3 4 04H 08H 0CH 10H
Function Control the master (global) interrupt (1=enabled; 0=disabled) Control the external interrupt (1=enabled; 0=disabled) Control the time base interrupt (1=enabled; 0=disabled) Control the real time clock interrupt (1=enabled; 0=disabled) External interrupt request flag (1=active; 0=inactive) Time base interrupt request flag (1=active; 0=inactive) Real time clock interrupt request flag (1=active; 0=inactive) Unused bit, read as 0 INTC0 (0BH) Register
Bit No. 0 1 2 3 4 5 6 7
Label ETI 3/4 3/4 3/4 TF 3/4 3/4 3/4 Unused bit, read as 0 Unused bit, read as 0 Unused bit, read as 0
Function Control the timer/event counter interrupt (1=enabled; 0=disabled)
Internal timer/event counter interrupt request flag (1=active; 0=inactive) Unused bit, read as 0 Unused bit, read as 0 Unused bit, read as 0 INTC1 (1EH) Register
Rev. 2.30
11
December 2, 2005
HT47C20L
The external interrupt request flag (EIF), real time clock interrupt request flag (RTF), time base interrupt request flag (TBF), enable external interrupt bit (EEI), enable real time clock interrupt bit (ERTI), enable time base interrupt bit (ETBI), and enable master interrupt bit (EMI) constitute an interrupt control register 0 (INTC0) which is located at 0BH in the data memory. The timer/event counter interrupt request flag (TF), enable timer/event counter interrupt bit (ETI) on the other hand, constitute an interrupt control register 1 (INTC1) which is located at 1EH in the data memory. EMI, EEI, ETI, ETBI, and ERTI are used to control the enabling/disabling of interrupts. These bits prevent the requested interrupt being serviced. Once the interrupt request flags (RTF, TBF, TF, EIF) are set, they remain in the INTC1 or INTC0 respectively until the interrupts are serviced or cleared by a software instruction. It is recommended that a program does not use the CALL subroutine within the interrupt subroutine. Interrupts often occur in an unpredictable manner or need to be serviced immediately in some applications. If only one stack is left, and enabling the interrupt is not well controlled, the original control sequence will be damaged once the CALL subroutine operates in the interrupt subroutine. Oscillator Configuration The HT47C20L provides one 32768Hz crystal oscillator for real time clock and system clock. The 32768Hz crystal oscillator still work at halt mode. The halt mode stop the system clock and T1 and ignores an external signal to conserve power. The real time clock comes from 32768Hz crystal and still works at halt mode. A 32768Hz crystal across OSC1 and OSC2 is needed to provide the feedback and phase shift needed for the oscillator, no other external components are needed.
OSC1 32768H z OSC2 C r y s ta l O s c illa to r fs ( s till w o r k s a t h a lt m o d e ) S y s te m c lo c k ( S to p s a t h a lt m o d e ) T1 ( s to p s a t h a lt m o d e )
Watchdog Timer - WDT The clock source of the WDT (fS) is implemented by a 32768Hz crystal oscillator. The timer is designed to prevent a software malfunction or sequence jumping to an unknown location with unpredictable results. The Watchdog Timer can be disabled by mask option. If the Watchdog Timer is disabled, all the executions related to the WDT result in no operation. The HALT instruction is executed, WDT still counts and can wake-up from halt mode due to the WDT time-out. The WDT overflow under normal operation will initialize chip reset and set the status bit TO. Whereas in the halt mode, the overflow will initialize a warm reset only the Program Counter and SP are reset to 0. To clear the contents of WDT, three methods are adopted, external reset (a low level to RES), software instruction, or a HALT instruction. The software instructions are of two sets which include CLR WDT and the other set - CLR WDT1 and CLR WDT2. Of these two types of instruction, only one can be active depending on the mask option - CLR WDT times selection option. If the CLR WDT is selected (i.e., CLR WDT times equal one), any execution of the CLR WDT instruction will clear the WDT. In case CLR WDT1 and CLR WDT2 are chosen (i.e. CLR WDT times equal two), these two instructions must be executed to clear the WDT; otherwise, the WDT may reset the chip because of the time-out. The WDT time-out period ranges from fS/215~fS/216. The CLR WDT or CLR WDT1 and CLRWDT2 instruction only clear the last two-stage of the WDT. Multi-function Timer The HT47C20L provides a multi-function timer for the WDT, time base and real time clock but with different time-out periods. The multi-function timer consists of a 7-stage divider and an 8-bit prescaler, with the clock source coming from the 32768Hz. The multi-function timer also provides a fixed frequency signal (fS/8) for the LCD driver circuits, and a selectable frequency signal (ranges from fS/22 to fS/29) for buzzer output by mask option.
32768Hz Crystal
3 2 7 6 8 H z C ry s ta l O S C
fS
D iv id e r
fS /2
8
P r e s c a le r W D T C le a r
CK R
T
CK R
T
T im e - o u t R e s e t fS /2 1 5 ~ fS /2 1 6
Watchdog Timer
Rev. 2.30
12
December 2, 2005
HT47C20L
Time Base The time base offers a periodic time-out period to generate a regular internal interrupt. Its time-out period ranges from fS/212 to fS/215 selected by mask option. If time base time-out occurs, the related interrupt request flag (TBF; bit 5 of INTC0) is set. But if the interrupt is enabled, and the stack is not full, a subroutine call to location 08H occurs. When the HALT instruction is executed, the time base still works and can wake up from halt mode. If the TBF is set 1 before entering the halt mode, the wake up function will be disabled. Real Time Clock - RTC The real time clock is operated in the same manner as the time base that is used to supply a regular internal interrupt. Its time-out period ranges from fS/28 to fS/215 by software programming. Writing data to RT2, RT1 and RT0 (bits 2, 1, 0 of RTCC;09H) yields various time-out periods. If a real time clock time-out occurs, the related interrupt request flag (RTF; bit 6 of INTC0) is set. But if the interrupt is enabled, and the stack is not full, a subroutine call to location 0CH occurs. The real time clock time-out signal can also be applied as a clock source of Timer/Event Counter A, so as to get a longer time-out period. RT2 0 0 0 0 1 1 1 1 RT1 0 0 1 1 0 0 1 1 RT0 0 1 0 1 0 1 0 1 RTC Clock Divided Factor 28 29 210 211 212 213 214 2
15
Power Down Operation - HALT The halt mode is initialized by the HALT instruction and results in the following.
* The 32768Hz crystal oscillator will still work but the
system clock and T1 will turn off.
* The contents of the on-chip RAM and registers remain
unchanged.
* The WDT will be cleared and recount again. * All I/O ports maintain their original status. * The PDF flag is set and the TO flag is cleared. * LCD driver is still running (by mask option). * The time base and real time clock will still work.
The system can leave the halt mode by means of an external reset, an interrupt, an external falling edge signal on port A or a WDT overflow. An external reset causes a device initialization and the WDT overflow performs a warm reset. Examining the TO and PDF flags, the reason for chip reset can be determined. The PDF flag is cleared when system power-up or executing the CLR WDT instruction and is set when the HALT instruction is executed. The TO flag is set if the WDT time-out occurs, and causes a wake-up that only resets the Program Counter and SP, the others maintain their original status. The port A wake-up and interrupt methods can be considered as a continuation of normal execution. Each bit in port A can be independently selected to wake up the device by mask option. Awakening from an I/O port stimulus, the program will resume execution of the next instruction. If awakening from an interrupt, two sequences may happen. If the related interrupt is disabled or the interrupt is enabled but the stack is full, the program will resume execution at the next instruction. If the interrupt is enabled and the stack is not full, a regular interrupt response takes place. If an interrupt request flag is set to 1 before entering the halt mode the wake-up function of the related interrupt will be disabled.
fS
D iv id e r
fS /2
8
P r e s c a le r L C D D r iv e r f S /8
M a s k O p tio n T im e B a s e In te r r u p t fS /2 1 2 ~ fS /2 1 5
B uzzer fS /2 2 ~ fS /2
9
Time Base
fS fS /2
8
D iv id e r RT2 RT1 RT0
P r e s c a le r fS /2 8 ~ fS /2 1 5 R e a l T im e C lo c k In te r r u p t
8 to 1 M ux.
Real Time Clock Rev. 2.30 13 December 2, 2005
HT47C20L
If the wake-up results from an interrupt acknowledgment, the actual interrupt subroutine execution will be delayed by more than one cycle. However, if the wake-up results in the next instruction execution, the execution will be performed immediately. To minimize power consumption, all the I/O pins should be carefully managed before entering the halt mode. Reset There are three ways in which a reset may occur.
* RES reset during normal operation * RES reset during halt mode * WDT time-out reset during normal operation * The LVR is enable and the VDD is lower then VLVR
To guarantee that the crystal oscillator has started and stabilized, the SST (system start-up timer) provides an extra delay of 8192 system clock pulses when the system powers up. The functional unit chip reset status are shown below. Program Counter Interrupt Prescaler, Divider WDT, Real Time Clock, Time Base Timer/event Counter Input/output Ports Stack Pointer
V
DD
000H Disabled Cleared Clear. After master reset, begin counting Off Input mode Points to the top of the stack
The WDT time-out during halt mode is different from other chip reset conditions, since it can perform a warm reset that just resets the Program Counter and SP leaving the other circuits in their original state. Some registers remain unchanged during other reset conditions. Most registers are reset to the initial condition when the reset conditions are met. By examining the PDF and TO flags, the program can distinguish between different chip resets. TO 0 u 0 1 1 PDF 0 u 1 u 1 RESET Conditions System power-up RES reset or LVR reset during normal operation RES reset or LVR reset wake-up from HALT mode WDT time-out during normal operation WDT wake-up from HALT mode
RES
Reset Circuit
H ALT W DT
RES
W DT T im e - o u t R eset E x te rn a l
W a rm
R eset
C o ld R eset SST 1 3 - b it R ip p le C o u n te r P o w e r - o n D e te c tio n
Note: u means unchanged
VDD RES S S T T im e - o u t C h ip R eset tS
ST
OSC1
Reset Configuration
Reset Timing Chart
Rev. 2.30
14
December 2, 2005
HT47C20L
The states of the registers are summarized in the following table: Register TMRAH TMRAL TMRC TMRBH TMRBL ADCR Program Counter MP0 MP1 ACC TBLP TBLH STATUS INTC0 INTC1 RTCC PA Note: Reset (power on) xxxx xxxx xxxx xxxx 0000 1--xxxx xxxx xxxx xxxx 1xxx --00 000H xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx --00 xxxx -000 0000 ---0 ---0 --xx 0111 1111 1111 WDT time-out RES reset (normal Operation) (normal operation) xxxx xxxx xxxx xxxx 0000 1--xxxx xxxx xxxx xxxx 1xxx --00 000H uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu --1u uuuu -000 0000 ---0 ---0 --xx 0111 1111 1111 xxxx xxxx xxxx xxxx 0000 1--xxxx xxxx xxxx xxxx 1xxx --00 000H uuuu uuuu uuuu uuuu uuuu uuuu uuu uuuu uuuu uuuu --uu uuuu -000 0000 ---0 ---0 --xx 0111 1111 1111 RES reset (HALT) xxxx xxxx xxxx xxxx 0000 1--xxxx xxxx xxxx xxxx 1xxx --00 000H uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu --01 uuuu -000 0000 ---0 ---0 --xx 0111 1111 1111 WDT time-out (HALT) uuuu uuuu uuuu uuuu uuuu u--uuuu uuuu uuuu uuuu uuuu --uu 000H* uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu --11 uuuu -uuu uuuu ---u ---u --uu uuuu uuuu uuuu
* refers to warm reset u means unchanged x means unknown
Timer/Event Counter One 16-bit timer/event counter with PFD output or two channels of RC type A/D converter is implemented in the HT47C20L. The ADC/TM bit (bit 1 of ADCR register) decides whether timer A and timer B are composed of one 16-bit timer/event counter or timer A and timer B are composed of two channels RC type A/D converter. The TMRAL, TMRAH, TMRBL, TMRBH composed of one 16-bit timer/event counter, when ADC/TM bit is 0. The TMRBL and TMRBH are timer/event counter preload registers for lower-order byte and higher-order byte respectively.
C lo c k T1 A /D C lo c k R e a l T im e C lo c k O u tp u t M U X TE TM TM TM TO N 2 1 0 P u ls e W id th M e a s u re m e n t M o d e C o n tro l TM R0 S y s te m
The timer/event counter clock source may come from system clock or T1 (system clock/4) or real time clock time-out signal or external source. Using external clock input allows the user to count external events, count external RC type A/D clock, measure time intervals or pulse widths, or generate an accurate time base. While using the internal clock allows the user to generate an accurate time base. There are six registers related to the timer/event counter operating mode. TMRAH ([20H]), TMRAL ([21H]), TMRC ([22H]), TMRBH ([23H]), TMRBL ([24H]) and ADCR ([25H]). Writing to TMRBL only writes the data into a low
D a ta B u s 1 6 - b it T im e r A O v e r flo w T R Q PFD
1 6 - b it T im e r B TM 2 TM 1 TM 0
R e lo a d P A 3 D a ta C T R L
Timer/Event Counter
Rev. 2.30
15
December 2, 2005
HT47C20L
Bit No. 0~2 3 4 Label 3/4 TE TON Unused bit, read as 0 To define the TMR active edge of the timer/event counter (0= active on low to high; 1= active on high to low) To enable/disable timer counting (0= disabled; 1= enabled) To define the operating mode (TM2, TM1, TM0) 000= Timer mode (system clock) 001= Timer mode (system clock/4) 010= Timer mode (real time clock output) 011= A/D clock mode (RC oscillation decided by ADCR register) 100= Event counter mode (external clock) 101= Pulse width measurement mode (system clock/4) 110= Unused 111= Unused TMRC (22H) Register byte buffer, and writing to TMRBH will write the data and the contents of the low byte buffer into the time/event counter preload register (16-bit) simultaneously. The timer/event counter preload register is changed by writing to TMRBH operations and writing to TMRBL will keep the timer/event counter preload register unchanged. Reading TMRAH will also latch the TMRAL into the low byte buffer to avoid the false timing problem. Reading TMRAL returns the contents of the low byte buffer. In other words, the low byte of the timer/event counter can not be read directly. It must read the TMRAH first to make the low byte contents of timer/event counter be latched into the buffer. If the timer/event counter is on, the TMRAH, TMRAL, TMRBH and TMRBL cannot be read or written to. To avoid conflicting between timer A and timer B, the TMRAH, TMRAL, TMRBH and TMRBL registers should be accessed with MOV instruction under timer off condition. The TMRC is the timer/event counter control register, which defines the timer/event counter options. The timer/event counter control register define the operating mode, counting enable or disable and active edge. Writing to timer B location puts the starting value in the timer/event counter preload register, while reading timer A yields the contents of the timer/event counter. Timer B is timer/event counter preload register. The TM0, TM1 and TM2 bits define the operation mode. The event count mode is used to count external events, which means that the clock source comes from an external (TMR) pin. The A/D clock mode is used to count external A/D clock, the RC oscillation mode is decided by ADCR register. The timer mode functions as a normal timer with the clock source coming from the internal selected clock source. Finally, the pulse width measurement mode can be used to count the high or low level duration of the external signal (TMR). The counting is based on the T1 (system clock/4). Rev. 2.30 16 In the event count, A/D clock or internal timer mode, once the timer/event counter starts counting, it will count from the current contents in the timer/event counter (TMRAH and TMRAL) to FFFFH. Once overflow occurs, the counter is reloaded from the timer/event counter preload register (TMRBH and TMRBL) and generates the corresponding interrupt request flag (TF; bit 4 of INTC1) at the same time. In the pulse width measurement mode with the TON and TE bits equal to 1, once the TMR has received a transient from low to high (or high to low if the TE bit is 0) it will start counting until the TMR returns to the original level and resets the TON. The measured result will remain in the timer/event counter even if the activated transient occurs again. In other words, only one cycle measurement can be done. Until setting the TON, the cycle measurement will function again as long as it receives further transient pulse. Note that in this operation mode, the timer/event counter starts counting not according to the logic level but according to the transient edges. In the case of counter overflow, the counter is reloaded from the timer/event counter preload register and issues interrupt request just like the other three modes. To enable the counting operation, the timer On bit (TON; bit 4 of TMRC) should be set to 1. In the pulse width measurement mode, the TON will automatically be cleared after the measurement cycle is completed. But in the other three modes, the TON can only be reset by instructions. The overflow of the timer/event counter is one of the wake-up sources and can also be applied as a PFD (programmable frequency divider) output at PA3 by mask option. No matter what the operation mode is, writing a 0 to ETI can disable the corresponding interrupt service. When the PFD function is selected, executing CLR PA.3 instruction to enable the PFD output and executing SET PA.3 instruction to disable the PFD output and PA.3 output low level. Function
5 6 7
TM0 TM1 TM2
December 2, 2005
HT47C20L
In the case of timer/event counter Off condition, writing data to the timer/event counter preload register also reloads that data to the timer/ event counter. But if the timer/event counter turns On, data written to the timer/event counter preload register is kept only in the timer/event counter preload register. The timer/event counter will still operate until overflow occurs. When the timer/event counter (reading TMRAH) is read, the clock will be blocked to avoid errors. As this may results in a counting error, this must be taken into consideration by the programmer. It is strongly recommended to load first the desired value into TMRBL, TMRBH, TMRAL, and TMRAH registers then turn on the related timer/event counter for proper operation. Because the initial value of TMRBL, TMRBH, TMRAL and TMRAH are unknown. If the timer/event counter is on, the TMRAH, TMRAL, TMRBH and TMRBL cannot be read or written to. Only when the timer/event counter is off and when the instruction MOV is used could those four registers be read or written to.
Example for Timer/event counter mode (disable interrupt): clr tmrc clr adcr.1 clr intc1.4 mov a, low (65536-1000) mov tmrbl, a mov a, high (65536-1000) mov tmrbh, a ; set timer mode ; clear timer/event counter interrupt request flag ; give timer initial value ; count 1000 time and then overflow
mov a, 00110000b tmrc, a
; timer clock source=T1 and timer on
p10: clr wdt snz intcl.4 jmp p10 ; polling timer/event counter interrupt request flag
clr intcl.4
; clear timer/event counter interrupt request flag ; program continue
Rev. 2.30
17
December 2, 2005
HT47C20L
A/D Converter Two channels of RC type A/D converter are implemented in the HT47C20L. The A/D converter contains two 16-bit programmable count-up counter and the timer A clock source may come from the system clock, T1 (system clock/4) or real time clock output. The timer B clock source may come from the external RC oscillator. The TMRAL, TMRAH, TMRBL, TMRBH are composed of the A/D converter when ADC/TM bit (bit 1 of ADCR register) is 1. The A/D converter timer B clock source may come from channel 0 (IN0 external clock input mode, RS0~CS0 oscillation, RT0~CS0 oscillation, CRT0~CS0 oscillation (CRT0 is a resistor), or RS0~CRT0 oscillation (CRT0 is a capacitor) or channel 1 (RS1~CS1 oscillation, RT1~CS1 oscillation or IN1 external clock input). The timer A clock source is from the system clock, T1 or real time clock prescaler clock output decided by TMRC register. There are six registers related to A/D converter, i.e., TMRAH, TMRAL, TMRC, TMRBH, TMRBL and ADCR. The internal timer clock is input to TMRAH and TMRAL, the A/D clock is input to TMRBH and TMRBL. The OVB/OVA bit (bit 0 of the ADCR register) decides whether timer A overflows or timer B overflows, then the TF bit is set and timer interrupt occurs. When the A/D converter mode timer A or timer B overflows, the TON bit is reset and stop counting. Writing TMRAH/TMRBH puts the starting value in the timer A/timer B and reading TMRAH/TMRBH gets the contents of the timer A/timer B. Writing TMRAL/TMRBL only writes the data into a low byte buffer, and writing TMRAH/TMRBH will write the data and the contents of the low byte buffer into the timer A/timer B (16-bit) simultaneously. The timer A/timer B is change by writing TMRAH/TMRBH operations and writing TMRAL/TMRBL will keep the timer A/timer B unchanged. R e a d i n g T M R A H / T M R B H w i l l a l so l a t ch t h e TMRAL/TMRBL into the low byte buffer to avoid the false timing problem. Reading TMRAL/TMRBL returns the contents of the low byte buffer. In other word, the low byte of timer A/timer B can not be read directly. It must read the TMRAH/TMRBH first to make the low byte contents of timer A/timer B be latched into the buffer. If the A/D converter timer A and timer B are counting, the TMRAH, TMRAL, TMRBH and TMRBL cannot be read or written to. To avoid conflicting between timer A and timer B, the TMRAH, TMRAL, TMRBH and TMRBL registers should be accessed with MOV instruction under timer A and timer B off condition. The bit4~bit7 of ADCR decides which resistor and capacitor compose an oscillation circuit and input to TMRBH and TMRBL. The TM0, TM1 and TM2 bits of TMRC define the clock source of timer A. It is suggested that the clock source of timer A use the system clock, instruction clock or real time clock prescaler clock. The TON bit (bit 4 of TMRC) is set 1, the timer A and timer B will start counting until timer A or timer B overflows, the timer/event counter generates the interrupt request flag (TF ; bit 4 of INTC1) and the timer A and timer B stop counting and reset the TON bit to 0 at the same time. If the TON bit is 1, the TMRAH, TMRAL, TMRBH and TMRBL cannot be read or written to. Only when the timer/event counter is off and when the instruction MOV is used could those four registers be read or written to.
Rev. 2.30
18
December 2, 2005
HT47C20L
Bit No. Label Function
0
In the RC type A/D converter mode, this bit is used to define the timer/event counter interrupt which comes from timer A overflow or timer B overflow. OVB/OVA (0= timer A overflow; 1= timer B overflow) In the timer/event counter mode, this bit is void. ADC/TM 3/4 To define 16-bit timer/event counter or RC type A/D converter is enable. (0= timer/event counter enable; 1= A/D converter is enable) Unused bits, read as 0 To define the A/D converter operating mode (M3, M2, M1, M0) 0000= IN0 external clock input mode 0001= RS0~CS0 oscillation (reference resistor and reference capacitor) 0010= RT0~CS0 oscillation (resistor sensor and reference capacitor) 0011= CRT0~CS0 oscillation (resistor sensor and reference capacitor) 0100= RS0~CRT0 oscillation (reference resistor and sensor capacitor) 0101= RS1~CS1 oscillation (reference resistor and reference capacitor) 0110= RT1~CS1 oscillation (resistor sensor and reference capacitor) 0111= IN1 external clock input mode 1XXX= Undefined mode ADCR (25H) Register
S1 S y s te m S y s te m RTC C lo c k S2 C lo c k /4 S3 O u tp u t TON O V B /O V A = 1 T im e r B R esetTO N T im e r A O V B /O V A = 0 In te rru p t
1 2~3
4 5 6 7
M0 M1 M2 M3
S12 S13
S4 IN 0 CS0
S5
S6 CRT0
S7 RS0
S8 RT0 IN 1 S9 CS1 S10 RS1 S11 RT1
TN2 0 0 0 O th e r
TN1 0 0 1
TN0 0 1 0
S1 1 0 0 0
S2 0 1 0 0
S3 0 0
M3 0 0
M2 0 0
M1 0 0
M0 0 1
S4 0 1 1
S5 0 0 0
S6 0 0
S7 0 1
S8 0 0
S9 0 0 0
S10 0 0 0 0
S11 0 0 0 0
S12 1 1
S13 0 0
1 0 0 0 0 0
0 0
0 1 1 0 1 0 1 0 1 1 1 1
1 0 1 0 1
0 1 0 0 1
0 1
1 0 1 0 1 0 0 1 0 0 0 0 0 1 1
1 0 0 0 0 0 1 0 0 0 0 0 0 1
0 0 0 1 0 0 0 0 0 1 0
0 0 1
N o te : 0 = o ff, 1 = o n
0 0 0 0 0 0 0
0
0 0 1 0 0
0 0
N o te : 0 = o ff, 1 = o n
RC Type A/D Converter
Rev. 2.30
19
December 2, 2005
HT47C20L
Example for RC type AD converter mode (Timer A overflow): clr tmrc clr adcr.1 clr intc1.4 mov a, low (65536-1000) mov tmrbl, a mov a, high (65536-1000) mov tmrbh, a ; set timer mode ; clear timer/event counter interrupt request flag ; give timer A initial value ; count 1000 time and then overflow
mov a, 00010010b mov adcr, a mov a, 00h mov tmrbl, a mov a, 00h mov tmrbh, a
; RS0~CS0; set RC type ADC mode; set Timer A overflow
; give timer B initial value
mov a, 00110000b mov tmrc, a
; timer A clock source=T1 and timer on
p10: clr wdt snz intcl.4 jmp p10 ; polling timer/event counter interrupt request flag
clr intcl.4
; clear timer/event counter interrupt request flag ; program continue
Rev. 2.30
20
December 2, 2005
HT47C20L
Example for RC type AD converter mode (Timer B overflow): clr tmrc clr adcr.1 clr intc1.4 a, 00h mov tmrbl, a a, 00h mov tmrbh, a ; set timer mode ; clear timer/event counter interrupt request flag ; give timer A initial value
mov a, 00010011b mov adcr,a
; RS0~CS0; set RC type ADC mode; set Timer B overflow
mov a, low (65536-1000) mov tmrbl, a mov a, high (65536-1000) mov tmrbh, a
; give timer B initial value ; count 1000 time and then overflow
mov a, 00110000b mov tmrc, a
; timer A clock source=T1 and timer on
p10: clr wdt snz intcl.4 jmp p10 ; polling timer/event counter interrupt request flag
clr intcl.4
; clear timer/event counter interrupt request flag ; program continue
Input/Output Ports There are 8-bit bidirectional input/output port and 4-bit input port in the HT47C20L, labeled PA and PB which are mapped to the data memory of [12H] and [14H] respectively. The high nibble of the PA is NMOS output and input with pull-high resistors. The low nibble of the PA can be used for input/output or output operation by selecting NMOS or CMOS output by mask option. Each bit on the PA can be configured as a wake-up input and the low nibble of the PA with or without pull-high resistors by mask option. PB can only be used for input operation, and each bit on the port is with pull high resistor. Both are for the input operation, these ports are non-latched, that is, the inputs should be ready at the T2 rising edge of the instruction MOV A, [m] (m=12H or 14H). For PA output operation, all data are latched and remain unchanged until the output latch is rewritten.
When the structures of PA are open drain NMOS type, it should be noted that, before reading data from the pads a 1 should be written to the related bits to disable the NMOS device. That is done first before executing the instruction MOV A, 0FFH and MOV [12H], A to disable the related NMOS device, and then MOV A, [12H] to get a stable data. After chip reset, these input lines remain at a high level or are left floating (by mask option). Some instructions first input data and then follow the output operations. For example, SET [m].i, CLR [m].i, CPL [m], CPLA [m] read the entire port states into the CPU, execute the defined operations (bit-operation), and then write the results back to the latches or to the accumulator. Each bit of the PA output latches can not use these instruction, which may change the input lines to output lines (when the input lines are at low level).
Rev. 2.30
21
December 2, 2005
HT47C20L
V
DD
V
DD
V
DD
V
DD
W EAK P u ll- u p D a ta B u s WR C h ip R e s e t D CK S Q M U X Q B Z O p tio n M ask O p tio n D a ta B u s P A 0 /B Z WR D CK S Q M U X Q B Z O p tio n M ask O p tio n
W EAK P u ll- u p
P A 1 /B Z
C h ip R e s e t
B Z S ig n a l M R e a d P a th X S y s te m M a s k O p tio n W a k e -u p M a s k O p tio n U M U X
R e a d P a th
S y s te m
W a k e -u p
PA0/BZ, PA1/BZ Input/Output Lines
IR DATA BUS WR C h ip R e s e t D CK S Q Q
O p tio n
VDD VDD W EAK P u ll- u p M a s k O p tio n P A 3 /P F D
M U X
M ask O p tio n
PFD
S ig n a l
M R e a d P a th X U
S y s te m
W a k e -u p M a s k O p tio n
PA3/PFD Input/Output Line
V
DD
W EAK P u ll- u p D a ta B u s W r ite C h ip R e s e t R e a d I/O S y s te m W a k e -u p M a s k O p tio n D CK S Q Q PA4~PA7
PA4~PA7 Input/Output Line
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December 2, 2005
HT47C20L
V V
DD DD
W EAK P u ll- u p M a s k O p tio n PA2
V
DD
D a ta B u s W r ite C h ip R e s e t
D CK S Q
Q
M ask O p tio n
W EAK P u ll- u p
R e a d D a ta D a ta B u s PB0~PB3
S y s te m
R e a d I/O W a k e -u p M a s k O p tio n
PB Input Lines
PA2 Input/Output Lines
LCD Display Memory The HT47C20L provides an area of embedded data memory for LCD display. The LCD display memory is designed into 204 bits. If the LCD selected 194 segments output, the 53H of the LCD display memory can not be accessed. This area is located from 40H to 53H of the RAM at Bank 1. Bank pointer (BP; located at 04H of the data memory) is the switch between the general data memory and the LCD display memory. When the BP is set 1 any data written into 40H~53H will effect the LCD display (indirect addressing mode using MP1). When the BP is cleared 0, any data written into 40H~53H has to access the general purpose data memory. The LCD display memory can be read and written only by indirect addressing mode using MP1. When data is written into the display data area, it is automatically read by the LCD driver which then generates the corresponding LCD driving signals. To turn the display On or Off, a 1 or a 0 is written to the corresponding bit of the display memory, respectively. The figure illustrates the mapping between the display memory and LCD pattern for the HT47C20L.
COM 0 1 2 3 40H 41H 42H 43H
LCD Driver Output The output number of the HT47C20L LCD driver can be 202 or 203 or 194 by mask option (i.e.1/2 duty, 1/3 duty or 1/4 duty). The bias type LCD driver is C type. If the 1/2 duty or 1/3 duty type is selected, the 1/2 bias type is selected. If the 1/4 duty type is selected, the 1/3 bias type is selected. A capacitor has to be connected between C1 and C2. The two kinds of the configurations of V1, V2 and V3 pins are as follows:
C1 C2 V1 V2 V3 V
DD
V1, V2, V3 Application Diagram
51H
52H
53H 0 1 2 3
B it
SEGMENT
0
1
2
3
17
18
19
Display Memory (Bank 1)
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D u r in g a R e s e t P u ls e : C O M 0 ,C O M 1 ,C O M 2 A ll L C D d r iv e r o u tp u ts N o r m a l O p e r a tio n M o d e : COM0 COM1 COM2 L C D s e g m e n ts o n C O M 0 ,1 ,2 s id e s b e in g u n lit O n ly L C D s e g m e n ts o n C O M 0 s id e b e in g lit O n ly L C D s e g m e n ts o n C O M 1 s id e b e in g lit O n ly L C D s e g m e n ts o n C O M 2 s id e b e in g lit L C D s e g m e n ts o n C O M 0 ,1 s id e s b e in g lit L C D s e g m e n ts o n C O M 0 ,2 s id e s b e in g lit L C D s e g m e n ts o n C O M 1 ,2 s id e s b e in g lit L C D s e g m e n ts o n C O M 0 ,1 ,2 s id e s b e in g lit H a lt M o d e : C O M 0 ,C O M 1 ,C O M 2 A ll L C D d r iv e r o u tp u ts
2VDD VDD VSS 2VDD VDD VSS 2V VD VS 2V VD VS D S S D DD DD D D D D D D D D D
2VD VDD VSS 2VD VDD VSS 2VD VDD VSS 2VD VDD VSS 2VD VDD VSS 2VD VDD VSS 2VD VDD VSS 2VD VDD VSS 2VD VDD VSS
2VDD VDD VSS 2VDD VDD VSS
LCD Driver Output (1/3 Duty, 1/2 Bias)
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3VDD 2VDD VDD COM0 VSS 3VDD 2VDD VDD COM1 VSS 3VDD 2VDD VDD COM2 VSS 3VDD 2VDD COM3 VDD VSS 3VDD 2VDD L C D s e g m e n ts O N C O M 2 s id e lig h te d VDD VSS
LCD Driver Output (1/4 Duty, 1/3 Bias)
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Voltage Low Detector The HT47C20L provides a voltage low detector for battery system application. If the battery voltage is lower than the specified value, the battery low flag (BLF; bit 5 of RTCC) is set. The specified value is 1.2V0.1V. The voltage low detector circuit can be turn On or Off by writing a 1 or a 0 to BON (bit 3 of RTCC register). A delay time of 1ms is required to monitor the BLF after setting the BON bit. The BLF is invalid when the BON is cleared as 0. The voltage low detector can be disabled by mask option. Buzzer HT47C20L provides a pair of buzzer output BZ and BZ, which share pins with PA0 and PA1 respectively, determined by mask option. Its output frequency can also be selected by mask option. When the buzzer function is selected, setting PA.0 and PA.1 0 simultaneously will enable the buzzer output and setting PA.0 1 will disable the buzzer output and setting PA.0 0 and PA.1 1 will only enable the BZ output and disable the BZ output. PA1 0 (CLR PA.1) 1 (SET PA.1) X PA0 0 (CLR PA.0) 0 (CLR PA.0) 1 (SET PA.0) Buzzer Enable Bit No. 0 1 2 3 4 5 6, 7 Label RT0 RT1 RT2 BON 3/4 BLF 3/4 Read/Write R/W Reset 1 1 1 0 3/4 X 3/4 Function 8 to 1 multiplexer control inputs to select the real time clock prescaler output Voltage low detector enable/disable control bit 0 indicates voltage detector is disabled 1 indicates voltage detector is enabled Unused bit, read as unknown Battery low flag 0 indicates that the voltage is not low 1 indicates that the voltage is low Unused bit, read as 0 RTCC (09H) Register Note: X means invalid Function PA0= BZ PA1= BZ PA0= BZ PA1= 0 PA0= 0 PA1= 0 Programmable Frequency Divider - PFD The PFD output shares pin with PA3 as determined by mask option. When the PFD option is selected, setting PA3 0 will enable the PFD output and setting PA3 1 will disable the PFD output and PA3 output at low level. PA3 0 (CLR PA.3) 1 (SET PA.3) PFD output frequency= 1 1 2 timer overflow period Low Voltage Reset - LVR The low voltage reset circuit is used to monitor the power supply of the device. If the power supply voltage of the device is lower than 1.1V0.1V, the device will automatically reset internally. It is enabled or disabled by mask option. The LVR includes the following specification:
* The low voltage (lower than 1.1V0.1V) must be main-
Function PA3= PFD Output PA3= 0
tained for over 1ms. If the low voltage state does not exceed 1ms, the LVR will ignore it and does not perform the reset function.
* The LVR uses the OR function with the external
RES signal to perform chip reset.
* During HALT mode, if the LVR occurs, the device will
wake-up and the PDF flag will be set as 1, the same as the RES reset.
R/W 3/4 R 3/4
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Mask Option The following shows many kinds of mask options in the HT47C20L. All these options should be defined in order to ensure proper system functioning. No. 1 2 Mask Option WDT enable or disable selection. WDT can be enabled or disabled by mask option. CLR WDT times selection. This option defines how to clear the WDT by instruction. One time" means that the CLR WDT can clear the WDT. Two times means that only if both of the CLR WDT1 and CLR WDT2 have been executed, then WDT can be cleared. Time base time-out period selection. The time base time-out period ranges from fS/212 to fS/215. fS stands for the 32768Hz frequency. Buzzer output frequency selection. There are eight types of frequency signals for the buzzer output: fS/22~fS/29. fS stands for the 32768Hz. Wake-up selection. This option defines the wake-up function activity. External I/O pins (PA NMOS output only) all have the capability to wake-up the chip from a halt mode by a following edge. Pull high selection. This option is to decide whether the pull high resistance is viable or not on the low nibble of the PA. PA CMOS or NMOS selection. The structure of the low nibble of the PA can be selected as CMOS or NMOS. When CMOS is selected, the related pins can only be used for output operations. When NMOS is selected, the related pins can be used for input or output operations. I/O pins share with other function selection. PA0/BZ, PA1/BZ: PA0 and PA1 can be set as I/O pins or buzzer outputs. PA3/PFD: PA3 can be set as I/O pins or PFD output. LCD common selection. There are three types of selection: 2 common (1/2 duty, 1/2 bias) 3 common (1/3 duty, 1/2 bias) or 4 common (1/4 duty, 1/3 bias). If the 4 common is selected, the segment output pin SEG19/COM3 will be set as a common output COM3. The low voltage reset and the low voltage detector enable or disable selection. There are three types of selection. The low voltage reset and the voltage detector are both enabled or both disabled or the low voltage reset is disabled but the voltage low detector is enabled. LCD on or LCD off at the halt mode selection. The LCD can be enable or disable at the halt mode by mask option.
3 4 5 6
7
8
9
10
11
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HT47C20L
Application Circuits
LCD Panel 0 .1 m F
OSC1 32768H z OSC2
SEG 0~18 CO M 0~3 C1 C2
V 100kW
DD
V1
0 .1 m F
V2
RES
0 .1 m F V
DD
0 .1 m F
V3 IN 0 CS0 CRT0 RT0 RS0 IN T TM R IN 1 CS1 RS1 RT1 PA0~PA7 PB0~PB3 H T47C 20L R
orC
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HT47C20L
Instruction Set Summary
Mnemonic Arithmetic ADD A,[m] ADDM A,[m] ADD A,x ADC A,[m] ADCM A,[m] SUB A,x SUB A,[m] SUBM A,[m] SBC A,[m] SBCM A,[m] DAA [m] Add data memory to ACC Add ACC to data memory Add immediate data to ACC Add data memory to ACC with carry Add ACC to data memory with carry Subtract immediate data from ACC Subtract data memory from ACC Subtract data memory from ACC with result in data memory Subtract data memory from ACC with carry Subtract data memory from ACC with carry and result in data memory Decimal adjust ACC for addition with result in data memory 1 1(1) 1 1 1(1) 1 1 1(1) 1 1(1) 1(1) Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV C Description Instruction Cycle Flag Affected
Logic Operation AND A,[m] OR A,[m] XOR A,[m] ANDM A,[m] ORM A,[m] XORM A,[m] AND A,x OR A,x XOR A,x CPL [m] CPLA [m] AND data memory to ACC OR data memory to ACC Exclusive-OR data memory to ACC AND ACC to data memory OR ACC to data memory Exclusive-OR ACC to data memory AND immediate data to ACC OR immediate data to ACC Exclusive-OR immediate data to ACC Complement data memory Complement data memory with result in ACC 1 1 1 1(1) 1(1) 1(1) 1 1 1 1(1) 1 Z Z Z Z Z Z Z Z Z Z Z
Increment & Decrement INCA [m] INC [m] DECA [m] DEC [m] Rotate RRA [m] RR [m] RRCA [m] RRC [m] RLA [m] RL [m] RLCA [m] RLC [m] Data Move MOV A,[m] MOV [m],A MOV A,x Bit Operation CLR [m].i SET [m].i Clear bit of data memory Set bit of data memory 1(1) 1(1) None None Move data memory to ACC Move ACC to data memory Move immediate data to ACC 1 1(1) 1 None None None Rotate data memory right with result in ACC Rotate data memory right Rotate data memory right through carry with result in ACC Rotate data memory right through carry Rotate data memory left with result in ACC Rotate data memory left Rotate data memory left through carry with result in ACC Rotate data memory left through carry 1 1(1) 1 1(1) 1 1(1) 1 1(1) None None C C None None C C Increment data memory with result in ACC Increment data memory Decrement data memory with result in ACC Decrement data memory 1 1(1) 1 1(1) Z Z Z Z
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HT47C20L
Mnemonic Branch JMP addr SZ [m] SZA [m] SZ [m].i SNZ [m].i SIZ [m] SDZ [m] SIZA [m] SDZA [m] CALL addr RET RET A,x RETI Table Read TABRDC [m] TABRDL [m] Miscellaneous NOP CLR [m] SET [m] CLR WDT CLR WDT1 CLR WDT2 SWAP [m] SWAPA [m] HALT Note: No operation Clear data memory Set data memory Clear Watchdog Timer Pre-clear Watchdog Timer Pre-clear Watchdog Timer Swap nibbles of data memory Swap nibbles of data memory with result in ACC Enter power down mode 1 1(1) 1(1) 1 1 1 1(1) 1 1 None None None TO,PDF TO(4),PDF(4) TO(4),PDF(4) None None TO,PDF Read ROM code (current page) to data memory and TBLH Read ROM code (last page) to data memory and TBLH 2(1) 2(1) None None Jump unconditionally Skip if data memory is zero Skip if data memory is zero with data movement to ACC Skip if bit i of data memory is zero Skip if bit i of data memory is not zero Skip if increment data memory is zero Skip if decrement data memory is zero Skip if increment data memory is zero with result in ACC Skip if decrement data memory is zero with result in ACC Subroutine call Return from subroutine Return from subroutine and load immediate data to ACC Return from interrupt 2 1(2) 1(2) 1(2) 1(2) 1(3) 1(3) 1(2) 1(2) 2 2 2 2 None None None None None None None None None None None None None Description Instruction Cycle Flag Affected
x: Immediate data m: Data memory address A: Accumulator i: 0~7 number of bits addr: Program memory address O: Flag is affected -: Flag is not affected
(1)
: If a loading to the PCL register occurs, the execution cycle of instructions will be delayed for one more cycle (four system clocks). : If a skipping to the next instruction occurs, the execution cycle of instructions will be delayed for one more cycle (four system clocks). Otherwise the original instruction cycle is unchanged. : and (2)
(2)
(3) (1) (4)
: The flags may be affected by the execution status. If the Watchdog Timer is cleared by executing the CLR WDT1 or CLR WDT2 instruction, the TO and PDF are cleared. Otherwise the TO and PDF flags remain unchanged.
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HT47C20L
Instruction Definition
ADC A,[m] Description Operation Affected flag(s) TO 3/4 ADCM A,[m] Description Operation Affected flag(s) TO 3/4 ADD A,[m] Description Operation Affected flag(s) TO 3/4 ADD A,x Description Operation Affected flag(s) TO 3/4 ADDM A,[m] Description Operation Affected flag(s) TO 3/4 PDF 3/4 OV O Z O AC O C O PDF 3/4 OV O Z O AC O C O PDF 3/4 OV O Z O AC O C O PDF 3/4 OV O Z O AC O C O PDF 3/4 OV O Z O AC O C O Add data memory and carry to the accumulator The contents of the specified data memory, accumulator and the carry flag are added simultaneously, leaving the result in the accumulator. ACC ACC+[m]+C
Add the accumulator and carry to data memory The contents of the specified data memory, accumulator and the carry flag are added simultaneously, leaving the result in the specified data memory. [m] ACC+[m]+C
Add data memory to the accumulator The contents of the specified data memory and the accumulator are added. The result is stored in the accumulator. ACC ACC+[m]
Add immediate data to the accumulator The contents of the accumulator and the specified data are added, leaving the result in the accumulator. ACC ACC+x
Add the accumulator to the data memory The contents of the specified data memory and the accumulator are added. The result is stored in the data memory. [m] ACC+[m]
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AND A,[m] Description Operation Affected flag(s) TO 3/4 AND A,x Description Operation Affected flag(s) TO 3/4 ANDM A,[m] Description Operation Affected flag(s) TO 3/4 CALL addr Description PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 Logical AND accumulator with data memory Data in the accumulator and the specified data memory perform a bitwise logical_AND operation. The result is stored in the accumulator. ACC ACC AND [m]
Logical AND immediate data to the accumulator Data in the accumulator and the specified data perform a bitwise logical_AND operation. The result is stored in the accumulator. ACC ACC AND x
Logical AND data memory with the accumulator Data in the specified data memory and the accumulator perform a bitwise logical_AND operation. The result is stored in the data memory. [m] ACC AND [m]
Subroutine call The instruction unconditionally calls a subroutine located at the indicated address. The program counter increments once to obtain the address of the next instruction, and pushes this onto the stack. The indicated address is then loaded. Program execution continues with the instruction at this address. Stack Program Counter+1 Program Counter addr
Operation Affected flag(s)
TO 3/4 CLR [m] Description Operation Affected flag(s) TO 3/4
PDF 3/4
OV 3/4
Z 3/4
AC 3/4
C 3/4
Clear data memory The contents of the specified data memory are cleared to 0. [m] 00H
PDF 3/4
OV 3/4
Z 3/4
AC 3/4
C 3/4
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CLR [m].i Description Operation Affected flag(s) TO 3/4 CLR WDT Description Operation Affected flag(s) TO 0 CLR WDT1 Description PDF 0 OV 3/4 Z 3/4 AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 Clear bit of data memory The bit i of the specified data memory is cleared to 0. [m].i 0
Clear Watchdog Timer The WDT is cleared (clears the WDT). The power down bit (PDF) and time-out bit (TO) are cleared. WDT 00H PDF and TO 0
Preclear Watchdog Timer Together with CLR WDT2, clears the WDT. PDF and TO are also cleared. Only execution of this instruction without the other preclear instruction just sets the indicated flag which implies this instruction has been executed and the TO and PDF flags remain unchanged. WDT 00H* PDF and TO 0*
Operation Affected flag(s)
TO 0* CLR WDT2 Description
PDF 0*
OV 3/4
Z 3/4
AC 3/4
C 3/4
Preclear Watchdog Timer Together with CLR WDT1, clears the WDT. PDF and TO are also cleared. Only execution of this instruction without the other preclear instruction, sets the indicated flag which implies this instruction has been executed and the TO and PDF flags remain unchanged. WDT 00H* PDF and TO 0*
Operation Affected flag(s)
TO 0* CPL [m] Description Operation Affected flag(s) TO 3/4
PDF 0*
OV 3/4
Z 3/4
AC 3/4
C 3/4
Complement data memory Each bit of the specified data memory is logically complemented (1s complement). Bits which previously contained a 1 are changed to 0 and vice-versa. [m] [m]
PDF 3/4
OV 3/4
Z O
AC 3/4
C 3/4
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CPLA [m] Description Complement data memory and place result in the accumulator Each bit of the specified data memory is logically complemented (1s complement). Bits which previously contained a 1 are changed to 0 and vice-versa. The complemented result is stored in the accumulator and the contents of the data memory remain unchanged. ACC [m]
Operation Affected flag(s)
TO 3/4 DAA [m] Description
PDF 3/4
OV 3/4
Z O
AC 3/4
C 3/4
Decimal-Adjust accumulator for addition The accumulator value is adjusted to the BCD (Binary Coded Decimal) code. The accumulator is divided into two nibbles. Each nibble is adjusted to the BCD code and an internal carry (AC1) will be done if the low nibble of the accumulator is greater than 9. The BCD adjustment is done by adding 6 to the original value if the original value is greater than 9 or a carry (AC or C) is set; otherwise the original value remains unchanged. The result is stored in the data memory and only the carry flag (C) may be affected. If ACC.3~ACC.0 >9 or AC=1 then [m].3~[m].0 (ACC.3~ACC.0)+6, AC1=AC else [m].3~[m].0 (ACC.3~ACC.0), AC1=0 and If ACC.7~ACC.4+AC1 >9 or C=1 then [m].7~[m].4 ACC.7~ACC.4+6+AC1,C=1 else [m].7~[m].4 ACC.7~ACC.4+AC1,C=C
Operation
Affected flag(s) TO 3/4 DEC [m] Description Operation Affected flag(s) TO 3/4 DECA [m] Description Operation Affected flag(s) TO 3/4 PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C O
Decrement data memory Data in the specified data memory is decremented by 1. [m] [m]-1
Decrement data memory and place result in the accumulator Data in the specified data memory is decremented by 1, leaving the result in the accumulator. The contents of the data memory remain unchanged. ACC [m]-1
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HT47C20L
HALT Description Enter power down mode This instruction stops program execution and turns off the system clock. The contents of the RAM and registers are retained. The WDT and prescaler are cleared. The power down bit (PDF) is set and the WDT time-out bit (TO) is cleared. Program Counter Program Counter+1 PDF 1 TO 0
Operation
Affected flag(s) TO 0 INC [m] Description Operation Affected flag(s) TO 3/4 INCA [m] Description Operation Affected flag(s) TO 3/4 JMP addr Description Operation Affected flag(s) TO 3/4 MOV A,[m] Description Operation Affected flag(s) TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 Directly jump The program counter are replaced with the directly-specified address unconditionally, and control is passed to this destination. Program Counter addr PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 PDF 1 OV 3/4 Z 3/4 AC 3/4 C 3/4
Increment data memory Data in the specified data memory is incremented by 1 [m] [m]+1
Increment data memory and place result in the accumulator Data in the specified data memory is incremented by 1, leaving the result in the accumulator. The contents of the data memory remain unchanged. ACC [m]+1
Move data memory to the accumulator The contents of the specified data memory are copied to the accumulator. ACC [m]
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MOV A,x Description Operation Affected flag(s) TO 3/4 MOV [m],A Description Operation Affected flag(s) TO 3/4 NOP Description Operation Affected flag(s) TO 3/4 OR A,[m] Description Operation Affected flag(s) TO 3/4 OR A,x Description Operation Affected flag(s) TO 3/4 ORM A,[m] Description Operation Affected flag(s) TO 3/4 PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 No operation No operation is performed. Execution continues with the next instruction. Program Counter Program Counter+1 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 Move immediate data to the accumulator The 8-bit data specified by the code is loaded into the accumulator. ACC x
Move the accumulator to data memory The contents of the accumulator are copied to the specified data memory (one of the data memories). [m] ACC
Logical OR accumulator with data memory Data in the accumulator and the specified data memory (one of the data memories) perform a bitwise logical_OR operation. The result is stored in the accumulator. ACC ACC OR [m]
Logical OR immediate data to the accumulator Data in the accumulator and the specified data perform a bitwise logical_OR operation. The result is stored in the accumulator. ACC ACC OR x
Logical OR data memory with the accumulator Data in the data memory (one of the data memories) and the accumulator perform a bitwise logical_OR operation. The result is stored in the data memory. [m] ACC OR [m]
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RET Description Operation Affected flag(s) TO 3/4 RET A,x Description Operation Affected flag(s) TO 3/4 RETI Description Operation Affected flag(s) TO 3/4 RL [m] Description Operation Affected flag(s) TO 3/4 RLA [m] Description Operation Affected flag(s) TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 Return from subroutine The program counter is restored from the stack. This is a 2-cycle instruction. Program Counter Stack
Return and place immediate data in the accumulator The program counter is restored from the stack and the accumulator loaded with the specified 8-bit immediate data. Program Counter Stack ACC x
Return from interrupt The program counter is restored from the stack, and interrupts are enabled by setting the EMI bit. EMI is the enable master (global) interrupt bit. Program Counter Stack EMI 1
Rotate data memory left The contents of the specified data memory are rotated 1 bit left with bit 7 rotated into bit 0. [m].(i+1) [m].i; [m].i:bit i of the data memory (i=0~6) [m].0 [m].7
Rotate data memory left and place result in the accumulator Data in the specified data memory is rotated 1 bit left with bit 7 rotated into bit 0, leaving the rotated result in the accumulator. The contents of the data memory remain unchanged. ACC.(i+1) [m].i; [m].i:bit i of the data memory (i=0~6) ACC.0 [m].7
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RLC [m] Description Operation Rotate data memory left through carry The contents of the specified data memory and the carry flag are rotated 1 bit left. Bit 7 replaces the carry bit; the original carry flag is rotated into the bit 0 position. [m].(i+1) [m].i; [m].i:bit i of the data memory (i=0~6) [m].0 C C [m].7
Affected flag(s) TO 3/4 RLCA [m] Description PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C O
Rotate left through carry and place result in the accumulator Data in the specified data memory and the carry flag are rotated 1 bit left. Bit 7 replaces the carry bit and the original carry flag is rotated into bit 0 position. The rotated result is stored in the accumulator but the contents of the data memory remain unchanged. ACC.(i+1) [m].i; [m].i:bit i of the data memory (i=0~6) ACC.0 C C [m].7
Operation
Affected flag(s) TO 3/4 RR [m] Description Operation Affected flag(s) TO 3/4 RRA [m] Description Operation Affected flag(s) TO 3/4 RRC [m] Description Operation PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C O
Rotate data memory right The contents of the specified data memory are rotated 1 bit right with bit 0 rotated to bit 7. [m].i [m].(i+1); [m].i:bit i of the data memory (i=0~6) [m].7 [m].0
Rotate right and place result in the accumulator Data in the specified data memory is rotated 1 bit right with bit 0 rotated into bit 7, leaving the rotated result in the accumulator. The contents of the data memory remain unchanged. ACC.(i) [m].(i+1); [m].i:bit i of the data memory (i=0~6) ACC.7 [m].0
Rotate data memory right through carry The contents of the specified data memory and the carry flag are together rotated 1 bit right. Bit 0 replaces the carry bit; the original carry flag is rotated into the bit 7 position. [m].i [m].(i+1); [m].i:bit i of the data memory (i=0~6) [m].7 C C [m].0
Affected flag(s) TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C O
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RRCA [m] Description Rotate right through carry and place result in the accumulator Data of the specified data memory and the carry flag are rotated 1 bit right. Bit 0 replaces the carry bit and the original carry flag is rotated into the bit 7 position. The rotated result is stored in the accumulator. The contents of the data memory remain unchanged. ACC.i [m].(i+1); [m].i:bit i of the data memory (i=0~6) ACC.7 C C [m].0
Operation
Affected flag(s) TO 3/4 SBC A,[m] Description Operation Affected flag(s) TO 3/4 SBCM A,[m] Description Operation Affected flag(s) TO 3/4 SDZ [m] Description PDF 3/4 OV O Z O AC O C O PDF 3/4 OV O Z O AC O C O PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C O
Subtract data memory and carry from the accumulator The contents of the specified data memory and the complement of the carry flag are subtracted from the accumulator, leaving the result in the accumulator. ACC ACC+[m]+C
Subtract data memory and carry from the accumulator The contents of the specified data memory and the complement of the carry flag are subtracted from the accumulator, leaving the result in the data memory. [m] ACC+[m]+C
Skip if decrement data memory is 0 The contents of the specified data memory are decremented by 1. If the result is 0, the next instruction is skipped. If the result is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Skip if ([m]-1)=0, [m] ([m]-1)
Operation Affected flag(s)
TO 3/4 SDZA [m] Description
PDF 3/4
OV 3/4
Z 3/4
AC 3/4
C 3/4
Decrement data memory and place result in ACC, skip if 0 The contents of the specified data memory are decremented by 1. If the result is 0, the next instruction is skipped. The result is stored in the accumulator but the data memory remains unchanged. If the result is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Skip if ([m]-1)=0, ACC ([m]-1)
Operation Affected flag(s)
TO 3/4
PDF 3/4
OV 3/4
Z 3/4
AC 3/4
C 3/4
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HT47C20L
SET [m] Description Operation Affected flag(s) TO 3/4 SET [m]. i Description Operation Affected flag(s) TO 3/4 SIZ [m] Description PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 Set data memory Each bit of the specified data memory is set to 1. [m] FFH
Set bit of data memory Bit i of the specified data memory is set to 1. [m].i 1
Skip if increment data memory is 0 The contents of the specified data memory are incremented by 1. If the result is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Skip if ([m]+1)=0, [m] ([m]+1)
Operation Affected flag(s)
TO 3/4 SIZA [m] Description
PDF 3/4
OV 3/4
Z 3/4
AC 3/4
C 3/4
Increment data memory and place result in ACC, skip if 0 The contents of the specified data memory are incremented by 1. If the result is 0, the next instruction is skipped and the result is stored in the accumulator. The data memory remains unchanged. If the result is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Skip if ([m]+1)=0, ACC ([m]+1)
Operation Affected flag(s)
TO 3/4 SNZ [m].i Description
PDF 3/4
OV 3/4
Z 3/4
AC 3/4
C 3/4
Skip if bit i of the data memory is not 0 If bit i of the specified data memory is not 0, the next instruction is skipped. If bit i of the data memory is not 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Skip if [m].i0
Operation Affected flag(s)
TO 3/4
PDF 3/4
OV 3/4
Z 3/4
AC 3/4
C 3/4
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SUB A,[m] Description Operation Affected flag(s) TO 3/4 SUBM A,[m] Description Operation Affected flag(s) TO 3/4 SUB A,x Description Operation Affected flag(s) TO 3/4 SWAP [m] Description Operation Affected flag(s) TO 3/4 SWAPA [m] Description Operation Affected flag(s) TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 PDF 3/4 OV O Z O AC O C O PDF 3/4 OV O Z O AC O C O PDF 3/4 OV O Z O AC O C O Subtract data memory from the accumulator The specified data memory is subtracted from the contents of the accumulator, leaving the result in the accumulator. ACC ACC+[m]+1
Subtract data memory from the accumulator The specified data memory is subtracted from the contents of the accumulator, leaving the result in the data memory. [m] ACC+[m]+1
Subtract immediate data from the accumulator The immediate data specified by the code is subtracted from the contents of the accumulator, leaving the result in the accumulator. ACC ACC+x+1
Swap nibbles within the data memory The low-order and high-order nibbles of the specified data memory (1 of the data memories) are interchanged. [m].3~[m].0 [m].7~[m].4
Swap data memory and place result in the accumulator The low-order and high-order nibbles of the specified data memory are interchanged, writing the result to the accumulator. The contents of the data memory remain unchanged. ACC.3~ACC.0 [m].7~[m].4 ACC.7~ACC.4 [m].3~[m].0
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SZ [m] Description Skip if data memory is 0 If the contents of the specified data memory are 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Skip if [m]=0
Operation Affected flag(s)
TO 3/4 SZA [m] Description
PDF 3/4
OV 3/4
Z 3/4
AC 3/4
C 3/4
Move data memory to ACC, skip if 0 The contents of the specified data memory are copied to the accumulator. If the contents is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Skip if [m]=0
Operation Affected flag(s)
TO 3/4 SZ [m].i Description
PDF 3/4
OV 3/4
Z 3/4
AC 3/4
C 3/4
Skip if bit i of the data memory is 0 If bit i of the specified data memory is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Skip if [m].i=0
Operation Affected flag(s)
TO 3/4 TABRDC [m] Description Operation Affected flag(s) TO 3/4 TABRDL [m] Description Operation Affected flag(s) TO 3/4
PDF 3/4
OV 3/4
Z 3/4
AC 3/4
C 3/4
Move the ROM code (current page) to TBLH and data memory The low byte of ROM code (current page) addressed by the table pointer (TBLP) is moved to the specified data memory and the high byte transferred to TBLH directly. [m] ROM code (low byte) TBLH ROM code (high byte)
PDF 3/4
OV 3/4
Z 3/4
AC 3/4
C 3/4
Move the ROM code (last page) to TBLH and data memory The low byte of ROM code (last page) addressed by the table pointer (TBLP) is moved to the data memory and the high byte transferred to TBLH directly. [m] ROM code (low byte) TBLH ROM code (high byte)
PDF 3/4
OV 3/4
Z 3/4
AC 3/4
C 3/4
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HT47C20L
XOR A,[m] Description Operation Affected flag(s) TO 3/4 XORM A,[m] Description Operation Affected flag(s) TO 3/4 XOR A,x Description Operation Affected flag(s) TO 3/4 PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 Logical XOR accumulator with data memory Data in the accumulator and the indicated data memory perform a bitwise logical Exclusive_OR operation and the result is stored in the accumulator. ACC ACC XOR [m]
Logical XOR data memory with the accumulator Data in the indicated data memory and the accumulator perform a bitwise logical Exclusive_OR operation. The result is stored in the data memory. The 0 flag is affected. [m] ACC XOR [m]
Logical XOR immediate data to the accumulator Data in the accumulator and the specified data perform a bitwise logical Exclusive_OR operation. The result is stored in the accumulator. The 0 flag is affected. ACC ACC XOR x
Rev. 2.30
43
December 2, 2005
HT47C20L
Package Information
64-pin QFP (1420) Outline Dimensions
C D 51 33 G H
I 52 32 F A B E
64
20 K a J 1 19
Symbol A B C D E F G H I J K a
Dimensions in mm Min. 18.80 13.90 24.80 19.90 3/4 3/4 2.50 3/4 3/4 1.15 0.10 0 Nom. 3/4 3/4 3/4 3/4 1 0.40 3/4 3/4 0.10 3/4 3/4 3/4 Max. 19.20 14.10 25.20 20.10 3/4 3/4 3.10 3.40 3/4 1.45 0.20 7
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December 2, 2005
HT47C20L
Holtek Semiconductor Inc. (Headquarters) No.3, Creation Rd. II, Science Park, Hsinchu, Taiwan Tel: 886-3-563-1999 Fax: 886-3-563-1189 http://www.holtek.com.tw Holtek Semiconductor Inc. (Taipei Sales Office) 4F-2, No. 3-2, YuanQu St., Nankang Software Park, Taipei 115, Taiwan Tel: 886-2-2655-7070 Fax: 886-2-2655-7373 Fax: 886-2-2655-7383 (International sales hotline) Holtek Semiconductor Inc. (Shanghai Sales Office) 7th Floor, Building 2, No.889, Yi Shan Rd., Shanghai, China 200233 Tel: 021-6485-5560 Fax: 021-6485-0313 http://www.holtek.com.cn Holtek Semiconductor Inc. (Shenzhen Sales Office) 5/F, Unit A, Productivity Building, Cross of Science M 3rd Road and Gaoxin M 2nd Road, Science Park, Nanshan District, Shenzhen, China 518057 Tel: 0755-8616-9908, 8616-9308 Fax: 0755-8616-9533 Holtek Semiconductor Inc. (Beijing Sales Office) Suite 1721, Jinyu Tower, A129 West Xuan Wu Men Street, Xicheng District, Beijing, China 100031 Tel: 010-6641-0030, 6641-7751, 6641-7752 Fax: 010-6641-0125 Holtek Semiconductor Inc. (Chengdu Sales Office) 709, Building 3, Champagne Plaza, No.97 Dongda Street, Chengdu, Sichuan, China 610016 Tel: 028-6653-6590 Fax: 028-6653-6591 Holmate Semiconductor, Inc. (North America Sales Office) 46729 Fremont Blvd., Fremont, CA 94538 Tel: 510-252-9880 Fax: 510-252-9885 http://www.holmate.com
Copyright O 2005 by HOLTEK SEMICONDUCTOR INC. The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek assumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable without further modification, nor recommends the use of its products for application that may present a risk to human life due to malfunction or otherwise. Holteks products are not authorized for use as critical components in life support devices or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information, please visit our web site at http://www.holtek.com.tw.
Rev. 2.30
45
December 2, 2005

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